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Data Sheet
Table 40. MASK1 Register (Address 0xE50B)
Bit
ADE7854/ADE7858/ADE7868/ADE7878
Location
0
1
Bit Mnemonic
NLOAD
FNLOAD
Default Value
0
0
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on total active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on fundamental active and reactive powers. Setting this bit to 1 does not
have any consequence for ADE7854 , ADE7858 , and ADE7868 .
2
3
4
5
6
7
VANLOAD
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
0
0
0
0
0
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on apparent power.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B current is
missing.
8
ZXTOIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C current is
missing.
9
ZXVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
voltage.
10
ZXVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
voltage.
11
ZXVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
voltage.
12
ZXIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
current.
13
ZXIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
current.
14
ZXIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
current.
15
RSTDONE
0
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
16
17
18
19
SAG
OI
OV
SEQERR
0
0
0
0
When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the
phases indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 41).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of
the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 41).
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of
the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 41).
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on
Phase A voltage is not followed by a negative-to-positive zero crossing on Phase B voltage,
but by a negative-to-positive zero crossing on Phase C voltage.
20
MISMTCH
0
When this bit is set to 1, it enables an interrupt when ISUM ? INWV > ISUMLVL is
greater than the value indicated in ISUMLVL register. Setting this bit to1 does not have any
consequence for ADE7854 and ADE7858 .
22:21
23
Reserved
PKI
00
0
Reserved. These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
24
PKV
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
31:25
Reserved
000 0000
Reserved. These bits do not manage any functionality.
Rev. H| Page 89 of 100
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